| Editor’s note: Here is another study from the same team in Tampere. The 2 studies handle two related topics – here is a brief description of their main content. 1. The exposed-datapath study (TCE/OpenASIP) focuses on designing entire customizable processors (ASIPs) from a single architecture description. It gives designers full control over the datapath—register files, function units and buses—so the compiler can explicitly schedule data movement. This approach is ideal when you want maximum microarchitectural freedom, deep optimisation for DSP/ML workloads, and a standalone programmable accelerator. It generates the whole processor, compiler and RTL together. 2. The RISC-V custom-instruction study takes a different path: instead of building a processor, it lets engineers add custom instructions to existing RISC-V cores without modifying the CPU. Using standard sockets (CV-X-IF and RoCC), the toolset automatically generates both coprocessor hardware and LLVM compiler plugins from one description. It prioritises verification safety, modularity and ease of adoption, showing strong speedups on CVA6 and Rocket. |
In short: TCE/OpenASIP builds processors; the CI study extends processors.
A research team at Tampere University—Pekka Jääskeläinen, Timo Viitanen, Jarmo Takala and Henri Berg—has developed a long-running open-source toolset that makes it easier to design highly customized processors for demanding computing tasks. Their work centres on the TTA-based Co-Design Environment (TCE) and the broader OpenASIP ecosystem, both designed to let engineers create tailored processors and the matching software tools from a single shared description.
The idea behind the toolset is straightforward: instead of beginning with fixed instruction formats, designers start by choosing the actual hardware resources—register files, specialised function units, interconnects and data paths—that suit their application. These resources form an exposed datapath processor, meaning the compiler can directly see and control how data moves between hardware units. This level of visibility gives the compiler fine-grained control to schedule operations efficiently, resulting in extremely dense, energy-efficient execution for workloads such as digital signal processing, image and video processing, software-defined radio and machine-learning inference.
According to the study, the toolset includes everything needed to design and test a custom processor: a retargetable compiler, an instruction-set simulator, and a Verilog/VHDL hardware generator, all driven from the same architecture description. This allows rapid exploration of design choices—engineers can add or remove function units, adjust register structures, or change dataflow paths and immediately evaluate the effects on performance. The authors note that the toolset has already been used in real silicon implementations and commercial-grade chips.
One of the toolset’s strengths is its practicality. It reduces verification effort compared with designing separate hardware accelerators, because the entire processor is generated systematically. It also provides clear benefits for companies that need programmable accelerators that remain flexible after manufacturing—something fixed-function accelerators cannot offer.
The study places this approach in context with modern RISC-V extension methods. While RISC-V sockets such as CV-X-IF and RoCC allow add-on accelerators to be attached to existing CPUs, TCE/OpenASIP instead creates a standalone programmable accelerator (ASIP) with maximum microarchitectural freedom. This makes it ideal for companies that need deep customization and precise control over scheduling, rather than minimal-risk add-ons to existing cores.
With decades of development behind it, Tampere University’s toolset remains one of the most influential open-source platforms for building domain-specific processors—enabling Nordic and global innovators to tailor computing hardware exactly to their application needs.
HW_SW Co-Design Toolset for Customization of Exposed Datapath Processors – Finland TU
Photo: Tampere University
